1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a Delay Locked Loop (hereinafter, referred to as DLL) for generating internal clock signals, a semiconductor memory device including the DLL and a locking operation method of the same.
2. Discussion of Related Art
Generally, a DLL corresponds to a semiconductor device for generating internal clock signals based on external clock signals in order to compensate for skew between the external clock signals and the internal clock signals, or between the external clock signals and output data. Accordingly, a synchronous semiconductor memory device for inputting or outputting data in synchronization with external clock signals includes a DLL as an internal clock generator. FIG. 1 schematically shows a conventional DLL and semiconductor memory device. Referring to FIG. 1, the DLL 10 includes an input buffer 11, a phase detector 12, a delay controller 13, a delay line 14, an output buffer 15 and a replica delay 16. The DLL 10 generates internal clock signals INCLK based on external clock signals EXCLK. Since a detailed operation of the DLL 10 can be easily understood by those skilled in the art, details will be omitted for convenience of a description. In the semiconductor memory device including the DLL 10, an output enable controller 20 receives the internal clock signals INCLK, and generates internal strobe signals DQSCLK based on the internal clock signals INCLK in response to output enable signals OUTEN. Further, a data output controller 30 receives the internal clock signals INCLK, and outputs output control signals DQCLK based on the internal clock signals INCLK in response to the output enable signals OUTEN. A Data Queue Strobe (hereinafter, referred to as DQS) driver 40 outputs data strobe signals DQS to an external device (not shown) in response to the internal strobe signals DQSCLK. Data output drivers 50 receive internal data signals INLDA1 to INLDAK (K is an integer), respectively, and outputs output data signals DQ1 to DQK to the external device in response to the output control signals DQCLK. As a result, the semiconductor memory device outputs the data strobe signals DQS and the output data signals DQ1 to DQK to the external device in synchronization with the external clock signals EXCLK. Accordingly, the external device receives the output data signals DQ1 to DQK in synchronization with the data strobe signals DQS. In the meantime, the replica delay 16 is designed to have delay time equal to time required until clock signals DLCLK outputted from the delay line 14 pass through the output buffer 15, the output enable controller 20 and the DQS driver 40, and are finally outputted as the data strobe signals DQS. Accordingly, the replica delay 16 delays the clock signals DLCLK during the same delay time as that due to the output path of the clock signals DLCLK, and outputs the delay signals as feedback clock signals FBCLK. The DLL 10 compares the phase of the feedback clock signals FBCLK with the phase of the external clock signals EXCLK, and generates the internal clock signals INCLK so that the data strobe signals DQS synchronizes with the external clock signals EXCLK, according to the comparison results. However, both the time (i.e. the delay time of the output enable controller 20) required when the internal clock signals INCLK pass through the output enable controller 20, and the delay time of the replica delay 16 may change according to conditions in manufacturing processes of the semiconductor memory device. When the delay time of the output enable controller 20 changes, the delay time of the replica delay 16 may differ from delay time due to an actual output path of the clock signals DLCLK. Specifically, the delay time of the replica delay 16 may be greater or less than delay time due to the output buffer 15, the output enable controller 20 and the DQS driver 40. As described above, when the delay time of the replica delay 16 does not coincide with the delay time due to the actual output path of the clock signals DLCLK, skew between the data strobe signals DQS/the output data signals DQ1 to DQK and the external clock signals may increase. Further, in the previously manufactured semiconductor memory device, it is very difficult to compensate for the skew increased due to difference between the delay time due to the actual output path of the clock signals DLCLK and the delay time of the replica delay 16. Furthermore, since the replica delay 16 must be designed to have the same delay time as that due to the actual output path of the clock signals DLCLK, the occupation area of the replica delay 16 increases. Therefore, the size of the DLL 10 may increase.